Call for papers
  12th International Workshop on Worst-Case Execution Time Analysis
                    Pisa, Italy, July 10, 2012

    http://www.artist-embedded.org/artist/WCET-2012.html (URL TO BE CONFIRMED)


                        In conjunction with
   the 24th Euromicro International Conference on Real-Time Systems (ECRTS)

http://ecrts.eit.uni-kl.de/ecrts12

GOALS

The workshop brings together academic researchers, technology makers and industry professionals who face the challenges of timing analysis in the development of
real-time systems.

The workshop adopts a highly interactive format with short, colloquial presentations and ample time for in-depth discussion of research results, new challenges,
problems and research directions.

TOPICS

The growing complexity of modern hardware, the advent of multicore processors, and the intricate organization of long-lived software systems challenge the
results achieved by timing analysis techniques, for users and researchers alike.

Design principles for the construction of timing-composable systems at both hardware and software level (compiler, runtime and development method) are
sought for timing analysis to respond to the emerging needs.

On this account, the workshop especially solicits contributions that:

a) discuss the limits of state-of-the-art timing analysis against aggressive hardware and software organizations, including but not limited to multicore
  systems, from both the research and the industrial perspectives;

b) present research results and research directions in timing analysis, and the system-level hardware and software support for it, that address the
  challenges ahead.

As part of and in addition to that, the workshop welcomes submissions that address:

- Novel approaches to WCET computation and strategies to reduce the analysis complexity, including time-predictable computer architectures and synergy
 with compilers

- Advances in tools for WCET analysis

- Capturing flow facts to feed flow analysis for WCET

- Needs and constraints stemming from current and future industrial development  process and schedule that timing analysis should best accommodate

- WCET-related analyses of code generated from design models

- Experience with the integration of WCET with schedulability analysis, as well as with the software and system development process

- Methods and benchmarks for WCET analysis evaluation.

SUBMISSION OF PAPER

Papers for the workshop must be written in English, should not exceed 10 pages in the required format, and should be submitted in PDF via the EasyChair
system at https://www.easychair.org/conferences/?conf=wcet2012 following the formatting instructions given at the workshop website.

The workshop proceedings with the revised, final version of the accepted papers will be published in Dagstuhl's OASIcs online proceedings series,
http://www.dagstuhl.de/en/publications/oasics/ , indexed, with ISBN.

IMPORTANT DATES

Submission deadline: 		April 20

Notification of acceptance:	May 20

Final version of papers due:	June 10

WCET Workshop:			July 10

ECRTS:				July 11-13

WORKSHOP CHAIR
Tullio Vardanega, University of Padova, Italy

PROGRAM COMMITTEE
Iain Bate, University of York, UK
Guillem Bernat, Rapita Systems Ltd, UK
Francisco Cazorla, Barcelona Supercomputing Center, Spain
Heiko Falk, Ulm University, Germany
Jan Gustafsson, Mälardalen University, Sweden
Kevin Hammond, University of St Andrews, UK
Chris Healy, Furman University, USA
Vesa Hirvisalo, Aalto University, Finland
Niklas Holsti, Tidorum Ltd, Finland
Raimund Kirner, University of Hertfordshire, UK
Björn Lisper, Mälardalen University, Sweden
Stefan Petters, ISEP - IPP, Portugal
Isabelle Puaut, University of Rennes 1 / IRISA, France
Martin Schoeberl, Technical University of Denmark
Christine Rochange, IRIT, France
Reinhard Wilhelm, Universitaet des Saarlandes, Germany

STEERING COMMITTEE
Guillem Bernat, Rapita Systems Ltd., UK
Jan Gustafsson, Mälardalen University, Sweden
Peter Puschner, Vienna University of Technology, Austria