Shanghai, China, May 21, 2012Co-located with 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2012), May 21-- May 25, 2012http://perlbench.hpc.cs.tsinghua.edu.cn/plc12

Call for Papers

Due to power and cooling constraints, recent performance improvements in both general-purpose and special-purpose processors have come primarily from increased on-chip parallelism rather than increased clock rates. On-chip parallelism with Multicore processors and GPU accelerators are now ubiquitous and have received significant attention in the past of a few years. Parallelism is therefore of considerable interest to a much broader group than developers of parallel applications for high-end supercomputers. This shift to an increasing on-chip parallelism will place new burdens on application software developers who are facing a daunting task of parallelizing general non-numerical applications and must have reasonable knowledge of multicore processor and GPU accelerator architectures, programming models, languages, compilers and new software tools for GPU and Multicore platforms. Several programming environments have recently emerged in response to the need to develop applications for GPUs and multi-core processors. This workshop provides a forum for the presentation of research on all aspects of GPU and multicore processors programming models, compiler optimizations, language extensions, and software tools for GPU and Multicore processor platforms.

Areas of interest include but are not limited to the following topics:

• Multicore processors and GPU accelerators
• Multicore and GPU Programming models: thread and task based models, data parallel models, stream programming
• Language extensions for GPU programming/environments:
• C/C++ extensions for GPU programming
• OpenMP extensions for Accelerator
• OpenCL
• CUDA
• CAL
• CAPS/HMPP
• Compiler optimizations and tuning for GPU accelerator and Multicore processors
• SIMDization/Vectorization
• Parallelization and locality optimizations
• Reducing synchronization and scheduling overheads on GPU and Multicore
• Tiling, parametric tiling and offloading
• Runtime systems for Multicore processor and GPU accelerators
• Debuggers, and performance analysis tools for multicore processor and GPU platforms
• Operating systems and virtual shared memory for CPU and GPU heterogeneous chip
• Software tools for discovering parallelism
• Application frameworks, design patterns, and domain-specific languages for developing manycore applications

Important Dates:

• Paper Submission Deadline: Jan 11th, 2012
• Paper Acceptance Notification: Feb 11th, 2012
• Camera Ready Due: Feb 21st, 2012
• Conference Date: May 21st, 2012

Submission Guidelines

Papers should present original research and should provide sufficient background material to make them accessible to the broader community. In addition, we solicit papers from practitioners describing problems and experiences building software tools for Multicore processors and GPU accelerators.

Full paper submissions should not exceed 10 pages in standard IEEE conference format. Papers should be submitted electronically through the workshop web site (to be set up).

Proceedings of accepted papers will be made available at the workshop. Selected papers will appear in the special issue of IEEE Journal (TBD later). Authors of accepted papers will have the option to decide if they want their papers to appear in this special issue. Submitted papers must not be simultaneously under review for any other conferences, and authors should point out any substantial overlap with their previously published or currently submitted work.

Committee

General Co-Chair:

• Jesse Fang, Intel
• Weimin Zheng, Tsinghua University

Steering Committee:

• Guang R. Gao, University of Delaware, US
• Bob Kuhn, Intel, US
• Weimin Zheng, Tsinghua University, China
• Jingling Xue, University of New South Wales, Australia
• Olivier Temam, INRIA

Program Co-Chair:

• Xinmin Tian, Intel
• Wenguang Chen, Tsinghua University

Program committee:

• Aart Bik, Google Inc. US
• James Beyer, Cray Inc. US
• Yeh-Ching Chung, National Tsinghua University, Taiwan
• Barbara Chapman, University of Houston, US
• Haibo Chen, Fudan University, China
• Bronis R. de Supinski, LLNL, US
• Zhiyuan Li, Purdue University, US
• Kai Lu, Nation University of Defense Technology, China
• Hongwei Wei, Jiangnan Institute of Computing Technology, China
• Chenggang Wu, Institute of Computing Technology, CAS, China
• Jingling Xue, University of New South Wales, Australia
• Olivier Temam, INRIA
• Albert Cohen, INRIA