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Call for Papers

18th Reconfigurable Architectures Workshop – RAW 2011
to be held with
The 25th IEEE International Parallel & Distributed Processing Symposium (IPDPS)
Anchorage, Alaska, USA, May 16-17, 2011

Submission deadline: December 3, 2010

Details at: http://www.ece.lsu.edu/vaidy/raw/
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The 18th Reconfigurable Architectures Workshop (RAW 2011) will be held in Anchorage, Alaska, USA in May 2011. RAW 2011 is associated with the 25th Annual International Parallel & Distributed Processing Symposium (IPDPS 2011) and is sponsored by the IEEE Computer Society's Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.
Run-Time Reconfiguration & Adaptive Computing:
Architectures, Algorithms, Technologies
Run-Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly alter (on the fly) the functionalities of its components and the interconnection between them to suit the problem. Key to this ability is reconfiguration handling and speed. Though theoretical models and algorithms for them have established reconfiguration as a very powerful computing paradigm, practical considerations make these models difficult to realize. On the other hand, commercially available devices (such as FPGAs and new coarse-/multi-grain devices) appear to have more room for exploiting run-time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essential to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2011 aims to provide a forum for creative and productive interaction between all these disciplines.
Topics of Interest
Authors are invited to submit manuscripts of original unpublished research in all areas of dynamic and run-time reconfiguration (foundations, algorithms, hardware architectures, devices, systems-on-chip (SoC), technologies, software tools, and applications). The topics of interest include, but are not limited to:
 
Models & Architectures
·    Theoretical Interconnect
and Computation Models
·    RTR Models and Systems
·    RTR Hardware Architectures
·    Optical Interconnect Models
·    Simulation and Prototyping
·    Bounds and Complexity Issues
Algorithms & Applications
·    Algorithmic Techniques
·    Mapping Parallel Algorithms
·    Distributed Systems & Networks
·    Fault Tolerance Issues
·    Wireless and Mobile Systems
·    Automotive Applications
·    Infotainment & Multimedia
·    Biology Inspired Applications
Design, Technologies & Tools
·     Configurable Systems-on-Chip
·     Energy Efficiency Issues
·     Devices and Circuits
·     Reconfiguration Techniques
·     High Level Design Methods
·     System Support
·     Adaptive Runtime Systems
·     Organic Computing
Important Dates:
Submission deadline:                       December 3, 2010
Notification of acceptance:               February 1, 2010
Camera-ready papers due:               February 21, 2011
 
 
Submission Guidelines:
Authors should submit their paper through the EDAS Conference Management System. You can register for an EDAS Account here.

All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript (not to exceed 8 pages of single spaced text, including figures and tables) or, in special cases, may be a summary of relevant work. Submissions should be in pdf-format (preferred), or alternatively in Postscript (level 2) format. Templates for paper preparation can be found at: http://www.ieee.org/web/publications/pubservices/confpub/AuthorTools/conferenceTemplates.html
IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by IEEE CS Press as a CD-ROM disk.
Organization:
Workshop Chair:                         Jürgen Becker, Karlsruhe Institute of Technology - KIT, Germany
                                                   becker@kit.edu
Program Co Chairs:                    Pascal Benoit, LIRMM, Montpellier, France
pascal.benoit@lirmm.fr
                                                   René Cumplido, INAOE, Puebla, México
rcumplido@inaoep.mx
Steering Chair:                           Viktor K. Prasanna, University of Southern California, USA      prasanna@ganges.usc.edu
Publicity Chair (USA):                 Ramachandran Vaidyanathan, Louisiana State University, USA
                                                   vaidy@ece.lsu.edu
Publicity Chair (Europe, Asia):    Reiner Hartenstein, Kaiserslautern University of Technology, Germany
                                                   reiner@hartenstein.de
Program Committee:
Shawki Areibi, University of Guelph
Sergio Bampi, Federal University of Rio Grande do Sul
Juergen Becker, University of Karlsruhe
Pascal Benoit, LIRMMM
Neil Bergmann, University of Queensland
Gordon Brebner, Xilinx, Inc.
Thomas Buechner, IBM Germany Research & Development
Oswaldo Cadenas, University of Reading
Fabio Campi, ST Microelectronics
Luigi Carro, Universidade Federal do Rio Grande
Ning Chen, PMC-Sierra
Peter Y. K. Cheung, Imperial College London
Rene Cumplido, INAOE
Omkar Dandekar, Intel Corporation
Oliver Diessel, University of New South Wales
Jean-Philippe, Diguet STICC UBS
Pedro Diniz, Insituto Superior Tecnico - UTL / INESC-ID
Adam Donlin, Xilinx
Hossam Elgindy, University of New South Wales
Suhaib Fahmy, Nanyang Technological University
Manfred Glesner, TU Darmstadt Germany
Guy Gogniat, STICC UBS
Yongfeng Gu, The Mathworks
Steven Guccione, Cmpware Inc.
Masanori Hariyama, Tohoku University
Reiner Hartenstein, University of Kaiserslautern
Ulrich Heinkel, Chemnitz University of Technology
Andreas Herkersdorf, Technische Universitat Muenchen
Christian Hochberger, Dresden University of Technology
Thomas Hollstein, Darmstadt University of Technology
Michael Heubner, Karlsruhe Institute of Technology
Alex Jones, University of Pittsburgh
Srinivas Katkoori, University of South Florida
Andreas Koch, Darmstadt University of Technology
Rainer Kress, Infineon Technologies
Helena Krupnova, ST Microelectronics
Loic Lagadec, University of Brest
Rudy Lauwereins, IMEC, Leuven
Philip Leong, University of Sydney
Patrick Lysaght, Xilinx, USA
Liam Marnane, UCC
Daniel Mesquita, Universidade Federal de Uberlandia
Fernando Moraes, PUCRS
Manuel Moreno, UPC
Carlos Morra, Siemens
Jerry Morris, US Army
Amar Mukherjee, University of Central Florida
Koji Nakano, Hiroshima University
Jose Nunez-Yanez, University of Bristol
Berna Ors, Istanbul Technical University
Jingzhao Ou, Xilinx
Fernando Pardo, University of Valencia
Ranjani Parthasarathi, Anna University
Cameron Patterson, Virginia Tech
Katarina Paulsson, Ericsson
Thilo Pionteck, University of Luebeck
Marco Platzner, University of Paderborn
Bernard Pottier, STICC CNRS
Ricardo Reis, Universidade Federal do Rio Grande do Sul
Marco Santambrogio, MIT
Ron Sass, University of North Carolina, Charlotte
Gilles Sassatelli, CNRS
Patrick Schaumont, Virginia Tech
Hartmut Schmeck, Karlsruhe Institute of Technology
Sakir Sezer, Queen's University, Belfast
Gerard Smit, University of Twente
Hayden So, University of Hong Kong
Gustavo Sutter, Universidad Autonoma de Madrid
Camel Tanougast, University Paul Verlaine - Metz
Juergen Teich, University of Erlangen-Nuremberg
Russell Tessier, University of Massachusetts
David Thomas, Imperial College
Lionel Torres, LIRMM, Montpellier
Jerry Trahan, Louisiana State University
Jim Torresen, University of Oslo
Ramachandran Vaidyanathan, Louisiana State University
Carlos Valderrama, University of Mons
Wim Vanderbauwhede, University of Glasgow
Milan Vasilko, Aeon Experts
Brian Veale, IBM
Martin Vorbach, PACT Informations technologies
Klaus Waldschmidt, University of Frankfurt
Norbert Wehn, University of Kaiserslautern