The 2011 ACM SIGPLAN Workshop on Memory Systems Performance & Correctness
(MSPC 2011)
June 5, 2006 - San Jose, California, USA
Co-located with PLDI/FCRC 2011
http://www.cs.wm.edu/~xshen/MSPC11

Call for Papers

Despite the capped growth of the peak CPU speed in chip multiprocessors, the memory wall problem becomes more serious and complex as more CPU/GPU cores are added, and the bandwidth resource becomes managed by multiple memory controllers and influenced by the constant cache interference among applications. Continuing the previous five successful workshops, MSPC 2011 will provide a forum for publishing and discussing the implications of the changes to both memory performance and correctness on various multi- and many-core systems---from supercomputers to servers to mobile devices---and the related software and hardware innovations. Areas of interest include but are not limited to the following topics:

* Analysis of memory systems performance (including power, bandwidth, and latency)
* Static and dynamic techniques for understanding and improving memory performance
* Memory hierarchy design for chip multiprocessors (CMPs)
* Hardware and software techniques for ensuring memory safety and detecting memory-related bugs (e.g., memory leaks, dangling pointers, out-of-bounds memory accesses, invalid C pointer arithmetic)
* Hardware and software memory models and their impact on programmability and performance
* Data race detection and debugging of programs with (possibly intentional) data races
* Managed memory and garbage collection optimizations
* Prefetching and compression to improve memory system performance
* Memory issues in accelerator-based computing (e.g., GPGPU)
* Memory system issues in embedded computers and tiny devices
* Impact of new storage class memory technologies (e.g., PCM, MRAM)
* Specifications of programming language (and library) shared memory semantics
* Power management and the impact on correctness/reliability

Software, hardware, and hybrid approaches are encouraged.  In addition, we solicit papers from practitioners describing problems and experiences with memory performance and correctness in specific application domains.

We encourage the submission of not-fully-polished but provocative short position papers (6 pages) or position abstracts (1-2 pages). Paper submissions should use standard ACM SIGPLAN conference format (10pt) (http://www.sigplan.org/authorInformation.htm). Copies of accepted papers will be made available at the workshop and published in the ACM digital library. Submitted papers must not be simultaneously under review for any other conference or journal, and authors should point out any substantial overlap with their previously published or currently submitted work.

Key Dates
* Abstract due: March 14, 2011
* Paper due: March 18, 2011 (11:59pm EDT)
* Notification: April 21, 2011
* Camera-ready submission: May 5, 2011

Organizing Committee

   General Chair
     Jeffrey Vetter, Oak Ridge National Lab & Georgia Tech
   Program Co-Chairs
     Madan Musuvathi, Microsoft Research
     Xipeng Shen, College of William & Mary
   PC Members
     Luis Ceze, U Washington
     Samuel Guyer, Tufts Univ
     Martin Hirzel, IBM Waston
     James Larus, Microsoft Research
     Milo Martin, U Pennsylvania
     Samuel Midkiff, Purdue Univ
     Naveen Muralimanohar, HP
     Todd Mytkowicz, Microsoft Research
     Satish Narayanasamy, U Michigan
     Dimitris Nikolopoulos, U Crete & FORTH
     Michelle M. Strout, Colorado State Univ

For details, please visit the workshop website:
http://www.cs.wm.edu/~xshen/MSPC11/.
============================================================


-- 
Madan Musuvathi, Microsoft Research
Xipeng Shen, The College of William and Mary
Program Co-Chairs, MSPC 2011